Configuration via Protocol (CvP) is a configuration scheme that allows you to configure the FPGA fabric via the PCI Express (PCIe*) interface for 14 nm Intel® Stratix® 10 FPGAs, 20 nm Intel® Arria® 10 FPGAs, and 28 nm Arria® V and Stratix® V FPGAs. The autonomous PCIe hard intellectual property (IP) allows the embedded PCIe core to operate before the FPGA is fully configured. This enables the FPGAs to easily meet the PCIe wake-up time requirement.