XC7Z100-2FFG900I – Integrated Circuits, Embedded, System On Chip (SoC)

Basic SoC architecture

A typical system-on-chip architecture consists of the following components:
- At least one microcontroller (MCU) or microprocessor (MPU) or digital signal processor (DSP), but there can be multiple processor cores.
- The memory may be one or more of RAM, ROM, EEPROM and flash memory.
- Oscillator and phase-locked loop circuitry for providing time pulse signals.
- Peripherals consisting of counters and timers, power supply circuits.
- Interfaces for different standards of connectivity such as USB, FireWire, Ethernet, universal asynchronous transceiver and serial peripheral interfaces, etc..
- ADC/DAC for conversion between digital and analogue signals.
- Voltage regulation circuits and voltage regulators.
Limitations of SoCs

Currently, the design of SoC communication architectures is relatively mature. Most chip companies use SoC architectures for their chip manufacturing. However, as commercial applications continue to pursue instruction co-existence and predictability, the number of cores integrated into the chip will continue to increase and bus-based SoC architectures will become increasingly difficult to meet the growing demands of computing. The main manifestations of this are
1. poor scalability. soC system design starts with a system requirements analysis, which identifies the modules in the hardware system. In order for the system to work correctly, the position of each physical module in the SoC on the chip is relatively fixed. Once the physical design has been completed, modifications have to be made, which can effectively be a redesign process. On the other hand, SoCs based on bus architecture are limited in the number of processor cores that can be extended on them due to the inherent arbitration communication mechanism of the bus architecture, i.e. only one pair of processor cores can communicate at the same time.
2. With a bus architecture based on an exclusive mechanism, each functional module in a SoC can only communicate with other modules in the system once it has gained control of the bus. As a whole, when a module acquires bus arbitration rights for communication, other modules in the system must wait until the bus is free.
3. Single clock synchronisation problem. The bus structure requires global synchronisation, however, as the process feature size becomes smaller and smaller, the operating frequency rises rapidly, reaching 10GHz later, the impact caused by the connection delay will be so serious that it is impossible to design a global clock tree, and because of the huge clock network, its power consumption will occupy most of the total power consumption of the chip.