Merrillchip New & Original in stock Electronic components integrated circuit IC DS90UB928QSQX/NOPB

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FPDLINK is a high-speed differential transmission bus designed by TI, mainly used to transmit image data, such as camera and display data. The standard is constantly evolving, from the original pair of lines transmitting 720P@60fps images to the current ability to transmit 1080P@60fps, with subsequent chips supporting even higher image resolutions. The transmission distance is also very long, reaching around 20m, making it ideal for automotive applications.

FPDLINK has a high-speed forward channel for transmitting high-speed image data and a small portion of control data. There is also a relatively low-speed backward channel for the transmission of reverse control information. The forward and backward communications form a bi-directional control channel, which leads to the clever design of the I2C in FPDLINK that will be discussed in this paper.

FPDLINK is used with a serializer and a deserializer paired together, the CPU can be connected to either the serializer or the deserializer, depending on the application. For example, in a camera application, the camera sensor connects to the serializer and sends data to the deserializer, while the CPU receives the data sent from the deserializer. In a display application, the CPU sends data to the serializer and the deserializer receives the data from the serializer and sends it to the LCD screen for display.

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The CPU's i2c can then be connected to the serializer or deserializer's i2c. The FPDLINK chip receives the I2C information sent by the CPU and transmits the I2C information to the other end via the FPDLINK. As we know, in the i2c protocol, the SDA is synchronized via SCL. In general applications, data is latched on the rising edge of SCL, which requires the master or slave to be ready for data on the falling edge of SCL. However, in FPDLINK, since FPDLINK transmission is timed, there is no problem when the master sends data, at most the slave receives the data a few clocks later than the master sends it, but there is a problem when the slave replies to the master, for example, when the slave responds to the master with an ACK when the ACK is transmitted to the master, it is already later than the time sent by the slave, i.e. it has already gone through the FPDLINK delay and may have missed the rising edge of the SCL.

Fortunately, the i2c protocol takes this situation into account. i2c spec specifies a property called i2c stretch, which means that the i2c slave can pull the SCL down before sending the ACK if it is not ready so that the master will fail when trying to pull the SCL up so that the master will keep trying to pull the SCL up and wait for the, Therefore when analyzing the i2c waveform on the FPDLINK Slave side, we will find that each time the slave address part is sent, there are only 8 bits, and the ACK will be responded later.

TI's FPDLINK chip takes full advantage of this feature, instead of simply forwarding the received i2c waveform (i.e. keeping the same baud rate as the sender), it retransmits the received data at the baud rate set on the FPDLINK chip. This is therefore important to note when analyzing the i2c waveform on the FPDLINK Slave side. The CPU i2c baud rate may be 400K, but the i2c baud rate on the FPDLINK slave side is 100K or 1M, depending on the SCL high and low settings in the FPDLINK chip.