LVDS Serializer 2975Mbps Automotive 40-Pin WQFN EP T/R DS90UB927QSQX/NOPB
Product Attributes
| TYPE | DESCRIPTION |
| Category | Integrated Circuits (ICs) |
| Mfr | Texas Instruments |
| Series | Automotive, AEC-Q100 |
| Package | Tape & Reel (TR)
Cut Tape (CT) Digi-Reel® |
| SPQ | 2500T&R |
| Product Status | Active |
| Function | Serializer |
| Data Rate | 2.975Gbps |
| Input Type | FPD-Link, LVDS |
| Output Type | FPD-Link III, LVDS |
| Number of Outputs | 13 |
| Number of Outputs | 1 |
| Voltage - Supply | 3V ~ 3.6V |
| Operating Temperature | -40°C ~ 105°C (TA) |
| Mounting Type | Surface Mount |
| Package / Case | 40-WFQFN Exposed Pad |
| Supplier Device Package | 40-WQFN (6x6) |
| Base Product Number | DS90UB927 |
1.
By analyzing the i2c waveform of the slave, you will also find a very interesting phenomenon, when reading the register data, the slave will first issue its waveform for pre-read, for example, to read the registered address 0x00 data, you will see on the waveform after the master issued the write register address 0x00, then will issue the slave address for reading (R/W = (R/W = 1), a slave will issue 8 SCL waveforms for pre-read immediately after the waveform is issued, and these 8 clocks are not corresponding on the master side the master will be issued later, so the slave is equivalent to issue first.
The design of this place is very clever because the i2c protocol stipulates that the i2c stretch can only occur in the ninth bit, that is, the ACK bit. the waveform is not allowed to be pulled, and no data is received from the slave at this point, so there is a problem.
TI's approach is that, since there is a write action in front, followed by a read slave address sent immediately after, it is clear that the registered address to be read is the one written in front, so the master will send a read slave address in the 9bit ACK pull while sending eight SCLs for register read and write, and then release the SCL, master detects the SCL release after The master detects that the SCL is released and retransmits the read data clock, at which point data is returned to the CPU.
2.
LVDS Common Terms or Terminology
1) Differential Pair: Refers to the LVDS signal transmission using two output drivers to drive two transmission lines, one carrying the signal and the other carrying its complementary signal. The signal required is the difference in voltage across the two transmission lines, which carry the signal information to be transmitted.
2) Signal pair: refers to the LVDS interface circuit where the output of each data transmission channel or clock transmission channel is two signals (positive and negative outputs)
3) Source: A device that generates a collection of text, graphics, images, audio, and video data.
4) Receiver (Sink): the device that processes and displays the data.
5) FPD-LINK: Flat Panel Display Link, a high-speed digital video interface specification based on the LVDS standard created by National Semiconductor in 1996 (acquired by Texas Instruments TI in 2011) to support data transfer from the graphics controller to the LCD panel.
6) GMSL: Gigabit Multimedia Serial Link, the LVDS signal transmission protocol format developed by Maxim based on the LVDS standard.
7) Forward channel: A high-speed data transmission channel from the Serializer to the Deserializer.
8) Backchannel: Also called Reverse channel, refers to the low-speed data transmission channel from the Deserializer to the Serializer.
