Electronic Components IC Chips Integrated Circuits XC7A75T-2FGG484I IC FPGA 285 I/O 484FBGA
Product Attributes
| TYPE | DESCRIPTION |
| Category | Integrated Circuits (ICs)EmbeddedFPGAs (Field Programmable Gate Array) |
| Mfr | AMD Xilinx |
| Series | Artix-7 |
| Package | Tray |
| Standard Package | 60 |
| Product Status | Active |
| Number of LABs/CLBs | 5900 |
| Number of Logic Elements/Cells | 75520 |
| Total RAM Bits | 3870720 |
| Number of I/O | 285 |
| Voltage – Supply | 0.95V ~ 1.05V |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 100°C (TJ) |
| Package / Case | 484-BBGA |
| Supplier Device Package | 484-FBGA (23×23) |
| Base Product Number | XC7A75 |
Adaptive devices are the ideal choice
Using Xilinx devices in next-generation security devices not only addresses throughput and latency issues, but other benefits include enabling new technologies such as machine learning models, Secure Access Service Edge (SASE), and post-quantum encryption.
Xilinx devices provide the ideal platform for hardware acceleration for these technologies, as performance requirements cannot be met with software-only implementations. Xilinx is continuously developing and upgrading IP, tools, software, and reference designs for existing and next-generation network security solutions.
In addition, Xilinx devices offer industry-leading memory architectures with flow classification soft search IP, making them the best choice for network security and firewall applications.
Using FPGAs as traffic processors for network security
Traffic to and from security devices (firewalls) is encrypted at multiple levels, and L2 encryption/decryption (MACSec) is processed at the link layer (L2) network nodes (switches and routers). Processing beyond the L2 (MAC layer) typically includes deeper parsing, L3 tunnel decryption (IPSec), and encrypted SSL traffic with TCP/UDP traffic. Packet processing involves the parsing and classification of incoming packets and the processing of large traffic volumes (1-20M) with high throughput (25-400Gb/s).
Due to the large number of computing resources (cores) required, NPUs can be used for relatively higher speed packet processing, but low latency, high-performance scalable traffic processing is not possible because traffic is processed using MIPS/RISC cores and scheduling such cores based on their availability is difficult. The use of FPGA-based security appliances can effectively eliminate these limitations of CPU and NPU-based architectures.
Application-level security processing in FPGAs
FPGAs are ideal for inline security processing in next-generation firewalls because they successfully meet the need for higher performance, flexibility, and low-latency operation. In addition, FPGAs can also implement application-level security functions, which can further save computing resources and improve performance.
Common examples of application security processing in FPGAs include
- TTCP offload engine
- Regular expression matching
- Asymmetric encryption (PKI) processing
- TLS processing
