10AX048H2F34E2SG 100% New & Original Own Stock Integrated Circuit High-Performance Clock Buffer Family

short description:

Arria 10 device family delivers higher performance than the previous generation of mid-range and high-end FPGA and offer ower efficiency attained through a comprehensive set of power-saving technologies. The Arria 10 devices are ideal for high performance, power-sensitive, midrange applications in diverse markets.

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Product Detail

Product Tags

Product Attributes

EU RoHS	Compliant
ECCN (US)	3A001.a.7.b
Part Status	Active
HTS	8542.39.00.01
Automotive	No
PPAP	No
Family Name	Arria® 10 GX
Process Technology	20nm
User I/Os	492
Number of Registers	727160
Operating Supply Voltage (V)	0.9
Logic Elements	480000
Number of Multipliers	2736 (18x19)
Program Memory Type	SRAM
Embedded Memory (Kbit)	28760
Total Number of Block RAM	1438
EMACs	3
Device Logic Units	480000
Device Number of DLLs/PLLs	12
Transceiver Channels	36
Transceiver Speed (Gbps)	17.4
Dedicated DSP	1368
PCIe	2
Programmability	Yes
Reprogrammability Support	Yes
Copy Protection	Yes
In-System Programmability	Yes
Speed Grade	2
Single-Ended I/O Standards	LVTTL\|LVCMOS
External Memory Interface	DDR3 SDRAM\|DDR4\|LPDDR3\|RLDRAM II\|RLDRAM III\|QDRII+SRAM
Minimum Operating Supply Voltage (V)	0.87
Maximum Operating Supply Voltage (V)	0.93
I/O Voltage (V)	1.2\|1.25\|1.35\|1.5\|1.8\|2.5\|3
Minimum Operating Temperature (°C)	0
Maximum Operating Temperature (°C)	100
Supplier Temperature Grade	Extended
Tradename	Arria
Mounting	Surface Mount
Package Height	2.8
Package Width	35
Package Length	35
PCB changed	1152
Standard Package Name	BGA
Supplier Package	FBGA
Pin Count	1152
Lead Shape	Ball

Product Introduction

Intel Arria 10 devices use a 20 nm ALM as the basic building block of the logic fabric. The ALM architecture is the same as the previous generation FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the device generations. The ALM uses an 8-input fracturable look-up table (LUT) with four dedicated registers to help improve timing closure in register-rich designs and achieve an even higher design packing capability than the traditional two-register per LUT architecture