LCMXO2-256HC-4TG100C Original and New With Competitive Price In Stock IC Supplier
Product Attributes
| Pbfree Code | Yes |
| Rohs Code | Yes |
| Part Life Cycle Code | Active |
| Ihs Manufacturer | LATTICE SEMICONDUCTOR CORP |
| Part Package Code | QFP |
| Package Description | LFQFP, |
| Pin Count | 100 |
| Reach Compliance Code | compliant |
| ECCN Code | EAR99 |
| HTS Code | 8542.39.00.01 |
| Samacsys Manufacturer | Lattice Semiconductor |
| Additional Feature | ALSO OPERATES AT 3.3 V NOMINAL SUPPLY |
| JESD-30 Code | S-PQFP-G100 |
| JESD-609 Code | e3 |
| Length | 14 mm |
| Moisture Sensitivity Level | 3 |
| Number of Dedicated Inputs | |
| Number of I/O Lines | |
| Number of Inputs | 55 |
| Number of Outputs | 55 |
| Number of Terminals | 100 |
| Operating Temperature-Max | 85 °C |
| Operating Temperature-Min | |
| Organization | 0 DEDICATED INPUTS, 0 I/O |
| Output Function | MIXED |
| Package Body Material | PLASTIC/EPOXY |
| Package Code | LFQFP |
| Package Equivalence Code | TQFP100,.63SQ |
| Package Shape | SQUARE |
| Package Style | FLATPACK, LOW PROFILE, FINE PITCH |
| Packing Method | TRAY |
| Peak Reflow Temperature (Cel) | 260 |
| Power Supplies | 2.5/3.3 V |
| Programmable Logic Type | FLASH PLD |
| Propagation Delay | 7.36 ns |
| Qualification Status | Not Qualified |
| Seated Height-Max | 1.6 mm |
| Supply Voltage-Max | 3.462 V |
| Supply Voltage-Min | 2.375 V |
| Supply Voltage-Nom | 2.5 V |
| Surface Mount | YES |
| Temperature Grade | OTHER |
| Terminal Finish | Matte Tin (Sn) |
| Terminal Form | GULL WING |
| Terminal Pitch | 0.5 mm |
| Terminal Position | QUAD |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Width | 14 mm |
Product Introduction
The Complex Programmable Logic Device (CPLD) is an application-specific Integrated Circuit (ASIC) in the LSI (Large Scale Integrated Circuit) Integrated Circuit). It is suitable for control intensive digital system design, and its delay control is convenient. CPLD is one of the fastest growing devices in integrated circuits.
Components of CPLD
CPLD is a complex programmable logic device with large scale and complex structure, which belongs to the range of large-scale integrated circuits.
CPLD has five main parts: logical array block, macro unit, extended product term, programmable wired array and I/O control block.
1. Logical Array Block (LAB)
A logical array block consists of an array of 16 macro cells, and multiple LABS are connected together by a programmable array (PIA) and a global bus
2. Macro unit
The macro unit in the MAX7000 series consists of three functional blocks: a logical array, a product selection matrix, and a programmable register.
3. Extended product term
One product term of each macro cell can be reversely sent back to the logical array.
4. Programmable wired array PIA
Each LAB can be connected to form the required logic through the programmable wired array. This global bus is a programmable channel that can connect any signal source in the device to its destination.
5. I/O control block
The I/O control block allows each I/O pin to be individually configured for input/output and bidirectional operation.
Comparison of CPLD and FPGA
Although both FPGA and CPLD are programmable ASIC devices and have many common characteristics, due to the differences in the structure of CPLD and FPGA, they have their own characteristics:
1.CPLD is more suitable for completing various algorithms and combinatorial logic, and FP GA is more suitable for completing sequential logic. In other words,FPGA is more suitable for flip-flop rich structure, while CPLD is more suitable for flip-flop limited and product term rich structure.
2.The continuous routing structure of CPLD determines that its timing delay is uniform and predictable, while the segmented routing structure of FPGA determines its delay unpredictability.
3.FPGA has more flexibility than CPLD in programming. CPLD is programmed by modifying the logic function with a fixed internal connection circuit, while FPGA is programmed by changing the wiring of the internal connection. FP GA can be programmed under a logic gate, while CPLD is programmed under a logic block.
4.The integration of FPGA is higher than that of CPLD, and it has more complex wiring structure and logic implementation.
5.CPLD is more convenient to use than FPGA. CPLD programming using E2PROM or FASTFLASH technology, no external memory chip, easy to use. However, the programming information of FPGA needs to be stored in external memory, and the use method is complicated.
6. CPLDS are faster than FPgas and have greater time predictability. This is because FPGas are gate-level programming and distributed interconnections are adopted between CLBS, while CPLDS are logic block-level programming and the interconnections between their logic blocks are lumped.
7．In the programming way,CPLD is mainly based on E2PROM or FLASH memory programming, programming times up to 10,000 times, the advantage is that the system power off the programming information is not lost. CPLD can be divided into two categories: programming on the programmer and programming on the system. Most of the FPGA is based on SRAM programming, the programming information is lost when the system is powered off, and the programming data needs to be written back to the SRAM from outside the device each time it is powered on. Its advantage is that it can be programmed any time, and it can be programmed quickly in the work, so as to achieve dynamic configuration at the board level and system level.
8．CPLD confidentiality is good,FPGA confidentiality is poor.
9.In general, the power consumption of CPLD is larger than that of FPGA, and the higher the integration degree, the more obvious.
